1. Field of Use
This invention relates to cache units utilized by a processing unit and more particularly to apparatus for replacing information within a cache unit.
2. Prior Art
As is well known, a cache unit is interposed between a data processing unit and a main store. Such arrangements improve the performance of the data processing unit by providing fast access to instructions and data stored in the cache unit. During normal operation, when the information requested by the processing unit is not in cache, the block containing the requested information is fetched from main store. When the cache unit is filled, new blocks replace old blocks of information resident therein. While different arrangements may be used to select the old block of information, a round robin arrangement has been found desirable because of its simplicity of operation and ease of implementation.
In such arrangements, the assignment of a group of locations is made sequentially. It is possible that the next location in the normal sequence may be unavailable for assignment because of the detection of errors being introduced into the data as a result of being stored in the cache unit. One prior art arrangement provides apparatus and method which eliminates the delay in assigning a location under such conditions. For further information regarding the prior art arrangement, reference may be made to the copending patent application of Charles P. Ryan, titled "A Cache Memory Location Selection Mechanism" bearing Ser. No. 858,575, filed on Dec. 8, 1977.
While the above arrangement provides for rapid determination of the next available sequential storage group in cache, the arrangement is unable to detect conflicts associated with the type of information being replaced. When such conflicts go undetected, this could result in a decrease in the processing unit's performance.
Accordingly, it is an object of the present invention to provide an improved arrangement for replacing old information within a cache unit.
It is a further object of the present invention to provide an arrangement for assigning groups of cache locations which will not result in a decrease of the processing unit's performance.